We offer a method of synthesis of logic networks in an arbitrary functionally complete basis, implementing given Boolean functions and allowing single diagnostic tests with small lengths regarding stuck-at and/or inverse faults at inputs and/or outputs of gates under certain initial conditions connected with existence of short single fault detection tests for logic networks in the same basis under the same faults. Based on this method, we obtain new upper bounds on lengths of minimal single diagnostic tests for logic networks in some bases under some faults of gates.

logic network, stuck-at fault, inverse fault, single fault detection test, single diagnostic test

Mathematical modelling in actual problems of science and technics

Popkov Kirill Andreevich,  ,  orcid.org/0000-0003-3763-4050,  KIAM RAS